The invention relates to a novel method of depositing a spacer film on a gate stack array in a semiconductor device. The invention also relates to a new spacer film for use in integrated circuits, and in particular, to spacer films with excellent resistivity to dry etchants and enhanced selectivity to wet etchants.
Referring to FIG. 1, there is shown a portion of an integrated circuit wafer 10 in an intermediate stage of DRAM fabrication. The integrated circuit wafer section 10 has a substrate 12 formed of a material such as silicon. Formed in and on the substrate 12 are field oxide regions 14 and transistor gate stacks 16. The gate stacks 16 have a spacer film 17 deposited thereon. Also shown in FIG. 1 are the active or doped regions 18 in the substrate 12. A first layer of insulating material 20, which is usually a type of glass oxide well known in the art, which for example, may comprise Boro-Phospho-Silicate Glass (BPSG) is also formed over the substrate and gate stacks 16. The first layer of insulating material 20 may, in actuality, be formed as one or more layers of insulating material of, for example, BPSG. Also shown in FIG. 1 is a second layer of insulating material 22 deposited over the first layer 22. Contact openings 24 are then formed through the insulative layers 20, 22 down to the doped regions 18. Openings 24 are formed using a patterned photoresist mask (not shown) which defines locations or areas to be etched, i.e. the openings. To form the contact opening, an etchant is applied to the insulating layers 20, 22. Dry etching techniques known in the art for performing a self-aligned contact (SAC) etching, are typically utilized for this purpose. Freon-containing gases, for example, are applied to the surface of the insulating layer 22 to form the opening 24. A non-exhaustive listing of such gases includes such as fluorinated hydrocarbons as CH2F2, CHF3, C2F6, C2HF5, and CH3F. The spacer film 17 protects the sides of the gate stacks 16 during the SAC dry etching process. After etching, the photoresist layer is removed. The dry etching step often leaves behind a layer of etch residue 26 in the contact opening 24, usually at the bottom and sides thereof. This etch residue is often comprised of a material such as a hydrocarbon polymer or residual silicon dioxide. The etch residue can interfere with the connection between the doped region 18 and a subsequently deposited conductive polyplug (not shown) in the contact opening 24.
To remove the etch residue 26 formed in the contact opening 24, a cleaning step is performed. This cleaning step is typically a wet etch process in which dilute acid material, preferably dilute fluorine-containing compounds such as dilute hydrofluoric acid (HF) or HF:TMAH (trimethylaluminum hydroxide), for example, are utilized to remove the etch residue 26. Desirably, the etch residue should be removed without eroding the spacer film 17 or the contact opening 24. The spacer film 17 protects the gate stack 16 from contact with a conductive polyplug, which is deposited within opening 24 and which is usually formed of a material such as doped polysilicon.
Silicon oxynitrides are desirable as the spacer film 17 since they typically form a lower stress film and have a lower dielectric constant than oxygen-free silicon nitride. Silicon oxynitrides have also demonstrated better barrier properties to dopant diffusion than pure silicon oxides. One of the drawbacks of using silicon oxynitride, however, is the wet etch rate of the material in dilute hydrofluoric (HF) acid and other fluorine-containing compounds which may be used in the aforementioned contact residue cleaning step. With silicon dioxide, the wet etch rate is very often too high causing erosion of the spacer film 17 by the etchant material as the etch residue, or polymer/residual silicon dioxide layer, is removed by the etchant. In certain instances, the etch rate of the spacer film can be as great as two times (2xc3x97) the etch rate for the polymer residue layer. It is desirable to have a spacer film that is resistant to etching so that the contact opening 24, and in particular the bottom surface thereof, can be cleaned with a material such as dilute HF or HF:TMAH etch while not eroding the spacer film 17. It is also desirable to have a spacer film that can be partially etched, if need be, to provide a more robust conductive plug contact with the substrate 12.
What is therefore needed in the art is a new method of forming a more robust and selective spacer film. What is also needed is a new spacer film which exhibits excellent resistivity to the dry etchants used to form contact openings, and which also exhibits lower etch rates in wet etchants than other spacer films currently available in the art.
The invention provides a method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device. The method involves depositing an oxynitride layer on the gate stack by contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen-containing compound and oxygen (O2) to form the silicon oxynitride spacer film. The stoicheometry and other parameters are controlled to provide a selective wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom/minute. In a preferred embodiment of the invention, there is silicon carbide incorporation in the spacer film for improved dry etch (SAC) resistance.
The invention further provides a silicon oxynitride spacer film useful for protecting a gate stack in a semiconductor device. The spacer film has a wet etch rate within the range of about 25 Angstroms/minute to less than or equal to about 1 Angstrom/minute. The spacer film furthermore exhibits a high refractive index and a low dielectric constant.
Also provided as part of the invention is a semiconductor device with at least one gate stack, and a spacer film deposited over the gate stack. The spacer film has a wet etch rate in fluorine-containing wet etchants within the range of about 25 Angstroms/minute to less than or equal to about 1 Angstrom/minute.
In still another aspect of the invention, there is provided an integrated circuit having a substrate with at least one gate stack formed thereon. A spacer film deposited on at least the sides of the gate stack has a wet etch rate in fluorine-containing wet etchant compounds within the range of about 25 Angstroms/minute to less than or equal to about 1 Angstrom/minute.
Also provided is a memory device having a memory cell containing an access transistor. The transistor includes a gate stack and a spacer film deposited on at least the sides of the gate stack. The spacer film has a wet etch rate in fluorine-containing wet etchant compounds within the range of about 25 Angstroms/minute to less than or equal to about 1 Angstrom/minute.
Additional advantages and features of the present invention will become more readily apparent from the following detailed description and drawings which illustrate various embodiments of the invention.